This invention relates to the improvement of a receiver in the field of radio communications.
Automatic Frequency Control (AFC) circuit using a pilot signal, an automatic frequency control circuit of a conventional automatic frequency control communication system, is set forth in xe2x80x9cAUTOMATIC FREQUENCY CONTROL CIRCUITxe2x80x9d in Japanese Unexamined Patent Application No. HEI08-330910. The conventional art is outlined below.
The configuration of a conventional AFC circuit is shown in FIG. 31, wherein, a frequency converter 3101, a pilot signal extraction circuit 3102, an arc tangent calculation circuit 3103, a phase-difference calculation circuit 3104, a linear approximation circuit 3105, a frequency-error calculation circuit 3106, a variable oscillator 3107, and a memory 3108 are illustrated.
The operation is explained next. A digital radio communication system is generally not free from frequency offset in received signals due to the difference in oscillation frequencies between the oscillators used by a transmitter and a receiver, due to temperature change and other factors (this is called as frequency offset). Frequency offset is also caused by the Doppler shift incurred on the mobile unit in mobile communications and on the satellite in satellite communications. Because frequency offset in the received signal can degrade bit error rate, the AFC circuit is applied to the receiver to compensate for the frequency offset in the received signals.
In FIG. 31, an input to the AFC circuit is a received signal having frequency offset. After the received signal is input to the AFC circuit, it is input to frequency converter 3101. Frequency converter 3101 then converts the received signal to an intermediate frequency. Being converted to an intermediate frequency, the received signal is output from the AFC circuit while a pilot signal is extracted by a pilot signal extraction circuit 3102. A pilot signal is a sequence whose modulation phase is already known to the receiver, and the phase information of the known sequence is already stored in memory 3108 of the receiver, and by comparing the phase information to the phase of the received pilot signal, the frequency error can be obtained disregarding the modulation phase.
The pilot signal extracted by pilot signal extraction circuit 3102 is operated by arc tangent calculation circuit 3103 to obtain its arc tangent. A phase of the pilot signal is obtained through the arc tangent calculation. The phase difference of the pilot signal and phase information stored in memory 3108 are calculated by phase difference calculation circuit 3104.
Linear approximation circuit 3105 regards the output from phase difference calculation circuit 3104 as the linear function of time, and approximates phase difference linearly. Frequency error calculation circuit 3106 calculates a frequency error based on the inclination of the output from linear approximation circuit 3105. Based on the frequency error output from frequency error calculation circuit 3106, variable oscillator 3107 controls the frequency to be provided for frequency converter 3101 so as to eliminate the frequency error.
Based on the frequency error in the received signal output from frequency converter 3101, variable oscillator 3107 controls the frequency to be provided for frequency converter 3101 to make frequency error zero. Thus, automatic frequency control is achieved.
For the above mentioned AFC circuit, in order for the receiver to obtain the frequency error without removing the modulation phase, a pilot signal having the phase information known to the receiver must be inserted in the transmission data. It is undesirable as it degrades throughput. In addition, such a technique requires a memory in the receiver to calculate a phase difference in the received known sequence. Thus, it is not desirable as an extended circuitry is required, which results in increased power consumption.
Another automatic frequency control circuit in the conventional automatic frequency control communication system is a non-linear AFC circuit, which is expounded in xe2x80x9cDIGITAL COMMUNICATIONS BY SATELLITExe2x80x9d (written by V. K. Bhargava, published by Jateck Publishing Co., on May 21, 1986). Given below is the explanation of this conventional art.
FIG. 32 is a configuration of the conventional AFC circuit, wherein, multipliers 3201 and 3202, a phase converter 3203, hard limiters 3204 and 3205, multipliers 3206 and 3207, and an adder 3208 are shown.
The operation is explained below. In FIG. 32, a reference carrier signal is branched out to two. One of which is input to multiplier 3202 and the other is input to phase converter 3203, where the reference carrier signal is phase shifted by xcfx80/2, and then input to multiplier 3201. Like the previously explained conventional automatic frequency control circuit, the received signal having frequency offset is input to the AFC circuit shown in FIG. 32. The received signal having frequency offset is multiplied by the reference carrier signal of the frequency roughly equals the received signal by multipliers 3201 and 3202.
Signals output from multipliers 3201 and 3202 are input to hard limiters 3204 and 3205 for sign determination. At multiplier 3206, the input to hard limiter 3205 is multiplied by the output from hard limiter 3204, while at multiplier 3207, the input to hard limiter 3204 is multiplied by the output from hard limiter 3205, respectively. Then at adder 3208, the output from multiplier 3206 is deducted from the output from multiplier 3207, to obtain a frequency error signal.
Let us assume that the received signal r (t) and the reference carrier signal R (t) are given by the expressions below.
r(t)=x(t)cos(xcfx89ct+xcex8i)+y(t)sin(xcfx89ct+xcex8i)
R(t)=cos(xcfx89ct+xcex80)
where, xcfx89c denotes a frequency of the received signal, xcex8i denotes a phase of the received signal, xcex80 denotes a phase of the reference carrier signal, x(t) denotes an amplitude of the real part of r(t), and y(t) denotes an amplitude of the imaginary part of r(t).
According to the foregoing xe2x80x9cDIGITAL COMMUNICATIONS BY SATELLITExe2x80x9d, the frequency error signal e(t) is expressed approximately using xcfx86=xcex8ixe2x88x92xcex80, as follows:
e(t)=xe2x88x92Kxcfx86(K being constant)
Then, assuming that the Binary Phase Shift Keying (BPSK) modulation is applied as the modulation method, a baseband signal diagram of a noise-free received signal is shown in FIG. 33. Let us now assume that the phase of a transmitted signal is 0, a real signal point is point A, and a received signal point is point C of FIG. 33. That is, xcex8i=xcex8, xcex80=0, and the error signal e(t) =xe2x88x92Kxcex8. The phase difference between the real signal point A and the received signal point C becomes a positive value, indicating the frequency of the reference signal is lower than the frequency of the received signal.
When the carrier/noise(CN) ratio of the received signal is low, the position of the received signal point is significantly deviated from its original point due to the influence of noise. The distance from the signal point B (having the opposite polarity to the signal point A) may become shorter than the distance from the real signal point A. The position of the received signal point deviated due to noise is assumed to be Cxe2x80x2 in FIG. 33. Because the distance between Cxe2x80x2 and B becomes shorter than the distance between signals Cxe2x80x2 and A, xcex8xe2x80x2 is detected instead of the real value xcex8 as the phase rotation distance stemling from the frequency offset. In the example shown in FIG. 33, xcex8 and xcex8xe2x80x2 differ not only in their values but also in their polarities.
When polarities of xcex8 and xcex8xe2x80x2 are different, the AFC circuit controls to increase the frequency offset rather than its designed purpose of eliminating the frequency offset. The AFC circuit has a certain pull-in range in controllable frequency offset depending on the modulation or phase detection method. The frequency offset can be compensated up to the range half the symbol rate when the BPSK modulation is applied as the modulation method, and only up to xc2xc when the Quadrature Phase Shift Keying (QPSK) modulation is applied. If the frequency offset exceeds the pull-in range, or when the frequency error varies depending on time due to the Doppler shift, etc., in addition to low CN ratio, the AFC circuit generates asynchronization, thereupon becomes unable to eliminate frequency offset, causing substantial degradation of the bit error rate.
And how the modulation phase affects in obtaining the frequency error will be discussed below.
If the modulation phase is either 0 or 1 in the binary PSK (BPSK), for instance, point A of FIG. 34 is transmitted when the modulation phase is xe2x80x9c0xe2x80x9d, and point B of FIG. 34 is transmitted when the modulation phase is xe2x80x9c1xe2x80x9d. It is assumed that these points rotate to Axe2x80x2 and Bxe2x80x2 due to the frequency offset and then be received. At this time, because the receiver does not know what the modulation phase (whether it is 0 or 1) is, if, for instance, point Axe2x80x2 is received, and if the modulation phase is assumed to be xe2x80x9c0xe2x80x9d, then the shift of the phase angle due to the frequency offset is xcex8, but if the modulation phase is assumed to be xe2x80x9c1xe2x80x9d, then the shift of the phase angle due to the frequency offset becomes (xcfx80+xcex8).
Axe2x86x92Axe2x80x2:xcex8
Axe2x86x92Bxe2x80x2:xcfx80+xcex8
Bxe2x86x92Bxe2x80x2:xcex8
Bxe2x86x92Axe2x80x2:xcfx80+xcex8
Under such circumstances, to determine the modulation phase, xe2x80x9cwhether or not the phase angle of the received signal is larger or smaller than xcfx80/2xe2x80x9d is used. That is, if the phase angle of the received signal is from 0 to xcfx80/2, the modulation phase is xe2x80x9c0xe2x80x9d, and the phase angle shift due to the frequency offset equals the phase angle of the received signal. Conversely, if the phase angle of the received signal is between xcfx80/2 and xcfx80, the modulation phase is xe2x80x9c1xe2x80x9d, and the phase angle shift due to the frequency offset equals xe2x80x9cphase angle of the received signalxe2x88x92xcfx80xe2x80x9d. This phase angle shift due to the frequency offset can be calculated by doubling the phase angle.
The double frequency multiplication, or the method of removing the modulation phase doubling the phase angle due to the frequency offset is explained next. FIG. 35 shows a block diagram for a double frequency multiplication. The AFC having a Phase Lock Loop (PLL) type feedback loop shown in FIG. 35 is designed to obtain the phase shift due to the frequency offset based on the phase difference obtained between the current data and the data of one-data time before. In concrete, in dotted part 3501 of FIG. 35, at D, the phase difference between the current data and the previous data delayed for one-data time period is obtained. In the example of FIG. 34, the output from dotted part 3501 is a vector having the phase angle of xcex8 or (xcfx80+xcex8).
The next dotted part 3502 is the removing part of the modulation phase. The real part (in-phase part) and the imaginary part (orthogonal part) of the vector having the phase angle xcex8 or (xcfx80+xcex8) are multiplied. Assuming the phase angle is xcfx86, then,
cos(xcfx86)xc3x97sin(xcfx86)=(1/2)sin(2xcfx86)
where, xcfx86 equals xcex8 or xcfx80+xcex8, but irrespective of the modulation phase, the sin value double the phase angle xcex8 is obtained because
xcex8xc3x972=2xcex8
(xcfx80+xcex8)xc3x972=2xcfx80+2xcex8=2xcex8
The assumption xe2x80x9cwhen xcex8 less than  less than 1, xcex8≈sin xcex8xe2x80x9d is applied to the output from dotted part 3502, and then the output from dotted part 3502 is divided by two. That is,
(1/2)sin(2xcfx86)
=(1/2)sin(2xcex8)
≈(1/2)xc2x72xcex8=xcex8
However, because only polarity is required for the PLL-type feedback loop illustrated in FIG. 35, the phase angle is calculated by simply multiplying the loop gain g. The double frequency multiplication shown in FIG. 35 allows the removal of the modulation phase by doubling the phase angle due to the frequency offset.
Problems to be Solved by the Invention
The automatic frequency control circuit in the conventional automatic frequency control communication system has a problem of throughput deterioration because a known sequence is inserted in transmission signals to detect frequency offset. Moreover, because the receiver needs a memory to store data corresponding to the known sequence, the circuitry expands and power consumption increases. If frequency offset is large, or if frequency offset varies depending on time in addition to low C/N ratio, the AFC circuit generates asynchronization, thereby the compensation for the frequency offset is disabled.
The present invention aims at overcoming the above-mentioned problems.
The objective of the present invention is to achieve a communication system which can obtain a frequency error without removing modulation phase in the AFC circuit and to eliminate the frequency offset of the received signal using the obtained frequency error in the system using the time diversity scheme.
Yet another objective of the present invention is to achieve a communication system which provides a stable AFC circuit even under low C/N ratio, by reducing frequency offset errors stemming from determination errors in the frequency errors caused from the determination errors of modulation phase in the system using the time diversity scheme.
Yet another objective of the present invention is to achieve a communication system which can obtain frequency errors without removing the modulation phase in the AFC circuit and eliminate the frequency offset of the received signal by feeding the obtained frequency errors back to an Intermediate Frequency (IF) circuit in a system using the time diversity scheme.
Yet another objective of the present invention is to achieve a communication system which can obtain frequency errors without removing modulation phase in the AFC circuit and eliminate frequency offset from received signals by feeding the obtained frequency errors back to a Radio Frequency (RF) oscillator in the system using the time diversity scheme.
Yet another objective of the present invention is to achieve a communication system that provides better bit error rate in the system using the time diversity scheme.
Still another objective of the present invention is to achieve an excellent hindrance-proof and interference-proof communication system using the time diversity scheme.
An automatic frequency control communication system may comprise a transmitter which inputs a transmission data, generates a delayed data giving a determined time delay to the transmission data, multiplexes the delayed data to no delayed data of the transmission data for generating a multiplexed data, modulates the multiplexed data using Phase Shift Keying (PSK) modulation for generating a transmission signal, and transmits the transmission signal, and a receiver which receives the transmission signal transmitted by the transmitter as a received signal, detects the delayed data and the no delayed data included in the received signal, compensates for a phase shift of the receiving signal based on the delayed data and the no delayed data, and demodulates data of the received signal based on the delayed data and the no delayed data.
The automatic frequency control communication system, wherein the transmitter may include a transmission delay unit for inputting the transmission data, giving the determined time delay to the input transmission data, and outputting the delayed data, a parallel-to-serial converter for converting the transmission data and the delayed transmission data from parallel to serial data, a PSK modulation unit for PSK modulating the parallel-to-serial converted data a frequency converter for converting a frequency of the PSK modulated data, and a transmission unit for transmitting the frequency-converted data, and wherein the receiver may include an oscillator for oscillating a radio frequency, a mixer for inputting the received signal and mixing the input receiving signal with an output from the oscillator to convert the received signal into an IF signal, an IF circuit for converting the output from the mixer into a baseband signal, an AFC circuit for eliminating a frequency offset from the output from the IF circuit, a defecter circuit for detecting the output from the AFC circuit, a serial-to-parallel converter for converting the output from the detector circuit into the received data corresponding to the transmission data of the transmitter and into a first delayed received data corresponding to the delayed transmission data of the transmitter, a received delay unit for giving the determined time delay to the received data and outputting a second delayed received data, a combination circuit for combining the first delayed received data with the second delayed received data, and a discriminator for discriminating a phase of the output from the combination circuit and outputting a demodulated data.
The automatic frequency control communication system, wherein the transmitter may include the transmission delay unit for inputting the transmission data, giving the determined time delay to the input transmission data and outputting the delayed transmission data, the parallel-to-serial converter for converting the transmission data and the delayed transmission data from parallel to serial data, the PSK modulation unit for PSK modulating the parallel-to-serial converted data, the frequency converter for converting a frequency of the PSK modulated data, and the transmission unit for transmitting the frequency-converted data, and wherein the receiver may include the oscillator for oscillating the radio frequency, the mixer for inputting the received signal and mixing the input received signal with the output from the oscillator to convert the received signal into the baseband signal, a baseband filter for getting the mixer output filtered, the AFC circuit for feeding a frequency control signal back to the oscillator to eliminate the frequency offset from the output from the baseband filter, the defecter circuit for detecting the output from the baseband filter, the serial-to-parallel converter for converting the output from the detector circuit into the received data corresponding to the transmission data of the transmitter and to the first delayed received data corresponding to the delayed transmission data of the transmitter from serial to parallel data, the received delay unit for giving the determined time delay to the received data and outputting the second delayed received data, the combination circuit for combining the first delayed received data with the second delayed received data, and the discriminator for discriminating the phase of the combination circuit and outputting the demodulated data.
The automatic frequency control communication system, wherein the transmitter includes a convolutional coder for inputting the transmission data, and convolutionally coding the input transmission data, the transmission delay unit for giving the determined time delay to the convolutionally coded transmission data, and outputting a delayed transmission data, the parallel-to-serial converter for converting the convolutionally coded transmission data and the delayed transmission data convolutionally coded and with the given delay into parallel to serial data, the PSK modulation unit for PSK modulating the parallel-to-serial converted data, the frequency converter for converting the frequency of the PSK modulated data, and the transmission unit for transmitting the frequency converted data, and wherein the receiver may include the oscillator for oscillating the frequency, the mixer for inputting the received signal, and mixing the received signal with the output from the oscillator to convert the received signal into the IF signal, the IF circuit for converting the mixer output into the baseband signal, the AFC circuit for eliminating the frequency offset from the IF circuit, the detector circuit for detecting the output from the AFC circuit, the serial-to-parallel converter for converting the output from the detector circuit into the received data corresponding to the transmission data of the transmitter and the first delayed received data corresponding to the delayed transmission data of the transmitter from serial to parallel data, the received delay units for giving the determined time delay to the received data, and outputting the second delayed received data, the combination circuit for combining the first delayed received data with the second delayed received data, and the maximum likelihood decoder for maximum likelihood decoding the output from the combination circuit.
The automatic frequency control communication system, wherein the AFC circuit may obtain a frequency error without removing a modulation phase in the output from the IF circuit, and eliminate the frequency offset by feeding a frequency error signal back to the IF circuit, and the detector circuit may detect the output from the IF circuit.
The automatic frequency control communication system, wherein the AFC circuit may obtain the frequency error without removing the modulation phase in the output from the IF circuit, and eliminate the frequency offset by feeding the frequency error signal back to the oscillator, and the detector circuit may detect the output from the IF circuit.
The automatic frequency control communication system, wherein the transmitter may include the convolutional coder for inputting the transmission data and convolutionally coding the transmission data, the transmission delay unit for giving the determined time delay to the convolutionally coded transmission data, and outputting the delayed transmission data, the parallel-to-serial converter for converting the convolutionally coded transmission data and the delayed transmission data which is convolutionally coded with the given delay from parallel into serial data, the PSK modulation unit for PSK modulating the parallel to serial converted data, the frequency converter for converting the frequency of the PSK modulated data, and the transmission unit for transmitting the frequency-converted data, and wherein the receiver may include the oscillator for oscillating the radio frequency, the mixer for inputting the received signal, and mixing the input received signal with the output from the oscillator to convert the received signal into the baseband signal, the baseband filter for getting the output from the mixer to be filtered, the AFC circuit for outputting the frequency control signal out of the output from the baseband filter, the detector circuit for detecting the output from the baseband filter, the serial-to-parallel converter for converting the output from the detector circuit into the received data corresponding to the transmission data of the transmitter and the first delayed received data corresponding to the delayed transmission data of the transmitter from serial into parallel data, the received delay unit for giving the received data the determined time delay and outputting the second delayed received data, the combination circuit for combining the first delayed received data with the second delayed received data, and the maximum likelihood decoder for decoding the output from the combination circuit in the maximum likelihood.
The automatic frequency control communication system, wherein the transmitter may be equipped with a spread circuit for spreading the spectrum of the PSK modulated transmission data, and the frequency converter may convert the frequency of the spread transmission data into spectrum by the spread circuit, and wherein the receiver may be equipped with an Inverse spread circuit for inversely spreading the spectrum of the output from the AFC circuit, and the detector circuit detects the output from the inversely spread circuit.
The automatic frequency control communication system, wherein the transmitter may have the spread circuit for spreading the spectrum of the transmission data converted from parallel to serial, and the PSK modulation unit may PSK modulate the transmission data whose spectrum has been spread by the spread circuit, and wherein the receiver may have the inverse spread circuit for spreading spectrum of the output from the detector circuit inversely, and wherein the serial-to-parallel converter may convert the output from the inverse spread circuit from serial to parallel data.
The automatic frequency control communication system, wherein the combination circuit of the receiver may perform an equal gain combination.
The automatic frequency control communication system, wherein the combination circuit of the receiver may perform a maximum ratio combination.
The automatic frequency control communication system, wherein the convolutional coder may input the transmission data, and convolutionally code the input transmission data in order to output the transmission data made up of a plurality of data sequences, the transmission delay unit may give the determined time delay to the transmission data corresponding to the data sequences in order to output the delayed transmission data, and the parallel-to-serial converter may convert the transmission data corresponding to the data sequences and the delayed transmission data from parallel into serial data, and wherein the serial-to-parallel converter may convert the output from the detector circuit into the received data corresponding to the transmission data corresponding to the data sequences and the first delayed received data corresponding to the delayed transmission data corresponding to the data sequences from serial to parallel data, the received delay unit outputs the second delayed received data to which the determined time delay may be given to the received data, the combination circuit may combine the first delayed received data and the second delayed received data, and the maximum likelihood coder may code the output from the combination circuit corresponding to the data sequences in the maximum likelihood in order to output the coded data.
The automatic frequency control communication system, wherein the convolutional coder may input the transmission data, and convolutionally code the input transmission data in order to output convolutionally coded data made up of the plurality of data sequences, the transmission delay unit may give the convolutionally coded data corresponding to each data sequence the first transmission delay time corresponding to the data sequences to output the first transmission data, and may give the convolutionally coded data corresponding to each data sequence the second transmission delay time corresponding to the data sequences to output the second transmission data, and the parallel-to-serial converter may convert the first transmission data and the second transmission data of the data sequences from parallel into serial data, and wherein the serial-to-parallel converter may convert the output from the detector circuit into the first received data corresponding to the first transmission data corresponding to the data sequences and the second received data corresponding to the second transmission data corresponding to the data sequences, the received delay unit may give the first received data corresponding to the data sequences the first receiving delay time corresponding to the data sequences in order to output the first delayed signal, and may give the second received data corresponding to the data sequences the second received delay time corresponding to the data sequences in order to output the second delayed signal, the combination circuit may combine the first delayed signal and the second delayed signal, and the maximum likelihood coder may code the output from the combination circuit corresponding to the data sequences in maximum likelihood in order to output the decoded data, and wherein a sum of the first transmission delay time and the first received delay time may equal each of the data sequence, and the sum of the second transmission delay time and the second received delay time corresponding to the data sequences may equal.
A communication method may comprise steps of inputting a transmission data, generating delayed data giving a determined time delay to the transmission data, multiplexing the delayed data to no delayed data of the transmission data for generating a multiplexed data modulating the multiplexed data using the Phase Shift Keying (PSK) modulation for generating a transmission signal, transmitting the transmission signal, received the transmission signal transmitted by the transmitter as a received signal, detecting the delayed data and the no delayed data included in the received signal, compensating for a phase shift of the received signal based on the delayed data and the no delayed data, and demodulating data of the received signal based on the delayed data and the no delayed data.